This invention relates to a mass production technique of a semiconductor integrated circuit device, and more particularly, to a technique effectively applicable to a semiconductor production process, in which when a large number of wafers are continuously processed over a plurality of steps, the process is carried out in a mass production line wherein the lithographic step of wafers on which a film containing a transition metal such as ruthenium (Ru) is deposited and the lithographic step of wafers belonging to other steps are commonly used.
In the industrial fields other than that of the manufacture of a semiconductor, there is known a technique wherein a platinum group element is dissolved in a dissolution solution and isolated for the purpose of collecting the platinum group element from wastes or the like.
Japanese Laid-open Patent Publication No. Hei 7-157832 (Ito et al.) discloses a technique of recovering noble metals, such as gold, platinum group elements and the like, from used electronic parts, noble metal-containing, wasted catalysts, and a used jewelry by dissolution thereof in a dissolving solution. For the dissolution of noble-metals, there is used a dissolving solution which is obtained by mixing an aqueous solution of an inter-halogen compound (e.g. ClF, BrF, BrCl, ICl, ICl3, IBr or the like) and an aqueous solution of a halogenated oxoacid (iodic acid, bromic acid, chloric acid or the like) at a ratio in the range of 1:9 to 9:1. The noble metal dissolved in the solution is first separated as a halogenated complex, to which a solution of a compound (e.g. sodium hydroxide, sodium borohydride, hydrazine or its salt, sulfurous acid or its salt, a bisulfite or the like) is then added, thereby collecting the metal.
Japanese Laid-open Patent Application No. Hei 7-224333 (Wada et al) discloses a technique of dissolving out, in the form of an aqueous solution, an alloy formed by nuclear fission and containing noble metals, such as ruthenium (Ru), rhodium (Rh), palladium (Pd) without undergoing such a pretreatment as by liquid metal extraction by immersing the alloy in a dissolving solution of hydroiodic acid (or hydrobromic acid), to which an iodine simple element is added. It is stated that the dissolving solution has a concentration of hydroiodic acid (or hydrobromic acid) ranging from 5 to 57 wt %, and a concentration of the added iodine simple element ranging from 0.01 to 0.5 moles per liter of the former aqueous solution.
In order to ensure an accumulated charge quantity of finely divided memory cells, a great capacitance DRAM (Dynamic Random Access Memory) of 1 Gbit or over has a capacitance insulating film of an information storage capacitor constituted of a high dielectric material such as an ABO3-type composite oxide having a specific inductive capacity of 100 or over, i.e. a perovskite composite oxide of BST (Ba, Sr) TiO3). For use as a capacitance insulating film material of the next generation, studies have been made on ferrodielectric materials having a perovskite crystal structure such as of PZT (PbZrxTi1xe2x88x92xO3), PLT (PbLaxTi1xe2x88x92xO3) PLZT, SBT, PbTiO3, SrTiO3 and BaTiO3.
Where such a high/ferrodielectric material is used for the capacitance insulating film of a capacitor, it is necessary that conductive films for upper and lower electrodes sandwiching the capacitance insulating film therebetween should be each made mainly of a metal having high affinity for the high/ferrodielectric material, e.g. a platinum group metal (e.g. Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), Ir (iridium) or Pt (platinum). Especially, ruthenium (Ru) is considered to be full of promise for use as an electrode material of a capacitor wherein the capacitance insulating film is constituted of such a high/ferrodielectric material because of its excellent etching controllability and film stability.
On the other hand, as a countermeasure for preventing an increase in wiring resistance caused by the scale down of a wiring width and the lowering of reliability in the field of high-speed logic LSI""s, there has now been introduced copper wirings buried according to a so-called Damascene method. In the method, wiring grooves (and through-holes) are formed in an insulating film deposited on a substrate, and a copper (Cu) film having an electric resistance lower than an Al film is deposited on the insulating film including the inner surfaces of the wiring grooves (and the through-holes), followed by removal of an unnecessary copper film outside of the wiring grooves by a chemical mechanical polishing (CMP) method, the introduction of the buried copper wirings is now under study not only in the field of logic LSD, but also in the field of memories such as DRAM.
However, in order to introduce newcomer transition metals, such as the above-mentioned platinum group metals, perovskite-type high/ferrodielectrics and copper, which have never been in use in known wafer processes, and materials comprising the transition metals, into a semiconductor production process, it is essential to take a measure for preventing wafers from contamination with these transition metals. Especially, a transition metal such as copper has a great coefficient of diffusion in silicon (Si) and readily arrives at a substrate when undergoing an annealing step (thermal treatment step), with the great apprehension that it gives a serious adversely influence on device characteristics even at a very small concentration.
For instance, in the manufacturing process of general-purpose LSI""s such as DRAM, a facility investment is suppressed to a minimum to reduce product costs, so that lithographic devices (such as a light exposure device and an EB exposure device), various types of inspection devices, and an annealing (thermal treating) device are commonly used in an initial element-forming step and a wiring step prior to the formation of a gate insulating film. These common devices are employed in the step of forming capacitors by use of such a newcomer material as set out hereinabove. More particularly, after transfer, from the common devices, of a wafer used for carrying out the capacitor-forming step, a fresh wafer used for carrying out the initial element-forming step or used for carrying out the wiring step is, in turn, transferred into the devices. In case where the buried copper wiring formed according to the Damascene method is provided as the wiring formed as an upper layer of the capacitor, a wafer having a copper film deposited on as an upper layer of the capacitor is transferred to the common devices for annealing (thermal treatment) after or prior to the transfer of another wafer to be subjected to other steps.
A film containing a platinum group metal, a perovskite-type high/ferrodielectric material or a transition metal such as copper, which has been deposited on the device side of a wafer according to a sputtering method or a CVD method, is also deposited on the outer marginal portions (edge portions) or the back side of the wafer. In this condition, when the wafer, from which the transition metal-containing film deposited on the outer edge portions or the back side of the wafer, is transferred to the common devices without removing the film to a satisfactory extent, a wafer stage, a wafer carrier, a conveyor and the like, which has come into contact with the outer edge portion or the back side of the wafer, are deposited on the surface thereof with the transition metal-containing film. This results in the contamination, with the transition metal, of a wafer which will be subsequently transferred to the common devices for performing lower layers steps (such as the step of forming an initial element and the wiring step prior to the formation of a gate insulating film).
Accordingly, in the mass production line for carrying out, by use of the common devices, the lithographic step for the wafer deposited thereon with a transition metal-containing film as stated above and the lithographic step for the wafers belonging to other steps including the lower layers steps, it is essential to provide a cleaning step of removing the transition metal-containing film deposited on the outer edge portions and the back side of a wafer prior to the transfer of the transition metal-containing film-deposited wafer.
However, a solution for dissolving, for example, ruthenium among the afore-indicated transition metals has not been found so that an effective cleaning method therefor has not been established yet. As having set out before, several types of solutions for dissolving platinum group metals have been proposed in the industrial fields other than that of the manufacture of semiconductor. However, these dissolving solutions are so low in dissolving rate of ruthenium that they cannot be used in the mass production line of semiconductor.
Another measure for preventing the contamination of a wafer with a transition metal is to provide an exclusive device for carrying out the lithographic step for the wafer deposited with a transition metal-containing film, separately from the common devices. Nevertheless, this is not of practical value from the standpoint of reduction in production cost.
An object of the invention is to provide a technique of reliably preventing the inconvenience of a wafer being contaminated with a transition metal when the wafer is subjected to an initial element formation step and a wiring step in the semiconductor mass production line wherein an initial element formation step and a wiring step, and a lithographic device, inspection devices, an annealing (thermal treating) device and the like in a transition metal-containing film processing step are commonly used prior to the formation of a gate insulating film.
This and other objects and features of the invention will become apparent from the description of the invention with reference to the accompanying drawings.
Of the embodiments disclosed in the invention, typical ones are briefly described or summarized below.
The mass production of a semiconductor integrated circuit device of the invention comprises the steps of:
(a) depositing a Ru film on individual wafers being in passage of a wafer process;
(b) removing the Ru film from outer edge portions on a containing an orthoperiodic acid, and
(c) subjecting the individual wafers, from which the Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step which is in common use with plural types of wafers belonging to lower layers steps.
The summary of the invention other than the above-stated one is briefly itemized as numbered below.
1. A mass production method of a semiconductor integrated circuit device comprising the steps of:
(a) depositing a platinum group metal film on a device side of a first wafer among a plurality of wafers passing through a wafer process;
(b) removing the platinum group metal film from outer edge portions of the device side or a back side of the first wafer, on which the platinum group metal film has been deposited;
(c) patterning, after the step (b), the platinum group metal film on the device side of the first wafer through an etching-resistant mask pattern formed in a lithographic step;
(d) depositing a film to be processed different in type from the platinum group metal film on a device side of a second wafer among the plurality of wafers passing through the wafer process; and
(e) patterning the film to be processed, which has been deposited on the device side of the second wafer, by the lithographic step.
2. Amass production method of a semiconductor integrated circuit device as recited in 1 above, characterized in that the platinum group metal film is made of a ruthenium film.
3. Amass production method of a semiconductor integrated circuit device as recited in 1 or 2 above, characterized in that the step of patterning the film to be processed is a lower layer step in comparison with the step of patterning the platinum group metal film.
4. A mass production method of a semiconductor integrated circuit device as recited in any one of 1 to 3 above, characterized in that the platinum group metal film is removed by use of a solution containing an orthoperiodic acid.
5. A mass production method of a semiconductor integrated circuit device as recited in any one of 1 to 4 above, characterized in that the platinum group metal film is removed by use of a solution containing an orthoperiodic acid and a second acid.
6. A mass production method of a semiconductor integrated circuit device as recited in 5 above, characterized in that the second acid is made of nitric acid.
7. A mass production method of a semiconductor integrated circuit device as recited in 6 above, characterized in that the solution has a concentration of orthoperiodic acid of 20 wt % to 40 wt %, and a concentration of nitric acid of 20 to 40 wt %.
8. A mass production method of a semiconductor integrated circuit device as recited in 6 above, characterized in that the solution has a concentration of orthoperiodic acid of 25 wt % to 35 wt %, and a concentration of nitric acid of 25 to 35 wt %.
9. A mass production method of a semiconductor integrated circuit device as recited in 5 above, characterized in that the second acid is made of acetic acid.
10. A mass production method of a semiconductor integrated circuit device as recited in any one of 1 to 9 above, characterized in that the platinum group metal film is removed, at least, from substantially an entire surface of the back side of the individual wafers and the outer edge portions of the device side.
11. A mass production method of a semiconductor integrated circuit device comprising the steps of:
(a) depositing a transition metal-containing film on a device side of a first wafer among a plurality of wafers passing through a wafer process;
(b) removing the transition metal-containing film from outer edge portions of the device side or a back side of the first wafer, on which the transition metal-containing film has been deposited;
(c) patterning, after the step (b), the transition metal-containing film on the device side of the first wafer through an etching-resistant mask pattern formed in a lithographic step;
(d) depositing a film to be processed different in type from the transition metal-containing film on a device side of a second wafer among the plurality of wafers passing through the wafer process; and
(e) patterning the film to be processed, which has been deposited on the device side of the second wafer, by the lithographic step.
12. A mass production method of a semiconductor integrated circuit device as recited in 11 above, characterized in that the transition metal-containing film is made of a perovskite-type high dielectric material or ferrodielectric material.
13. A mass production method of a semiconductor integrated circuit device as recited in 12 above, characterized in that the perovskite-type high dielectric material or ferrodielectric material is made of BST.
14. A mass production method of a semiconductor integrated circuit device as recited in 11 above, characterized in that the perovskite-type high dielectric material or ferrodielectric material is PZT, PLT, PLZT, SBT, PbTiO3, SiTiO3 or BaTiO3.
15. A mass production method of a semiconductor integrated circuit device as recited in 11 above, characterized in that the transition metal is made of copper.
16. A mass production method of a semiconductor integrated circuit device comprising the steps of:
(a) depositing a Ru film on a device side of a first wafer among a plurality of wafers passing through a wafer process;
(b) removing the Ru film from outer edge portions of the device side or a back side of the first wafer, on which the Ru film has been deposited;
(c) patterning, after the step (b), the Ru film on the device side of the first wafer through an etching-resistant mask pattern formed in a lithographic step, thereby forming a capacitor electrode;
(d) depositing a film to be processed different in type from the Ru film on a device side of a second wafer among the plurality of wafers passing through the wafer process; and
(e) patterning the film to be processed, which has been deposited on the device side of the second wafer, by the lithographic step.
17. A mass production method of a semiconductor integrated circuit device as recited in 16 above, characterized in that the step of pattering the film to be processed is a lower layer step downstream of or in comparison with the step of patterning the Ru film.
18. A mass production method of a semiconductor integrated circuit device as recited in 16 or 17 above, characterized in that the Ru film is removed by use of a solution containing orthoperiodic acid.
19. A mass production method of a semiconductor integrated circuit device as recited in 16 or 17 above, characterized in that the Ru film is removed by use of a solution containing an orthoperiodic acid and a second acid.
20. A mass production method of a semiconductor integrated circuit device as recited in 19 above, characterized in that the second acid is made of nitric acid.
21. A mass production method of a semiconductor integrated circuit device as recited in 20 above, characterized in that the solution has a concentration of orthoperiodic acid of 20 wt % to 40 wt %, and a concentration of nitric acid of 20 to 40 wt %.
22. A mass production method of a semiconductor integrated circuit device as recited in 20 above, characterized in that the solution has a concentration of orthoperiodic acid of 25 wt % to 35 wt %,-and a concentration of nitric acid of 25 to 35 wt %.
23. A mass production method of a semiconductor integrated circuit device comprising the steps of:
(a) depositing a Ru film on a device side of a first wafer among a plurality of wafers passing through a wafer process;
(b) removing the Ru film from outer edge portions of the device side or a back side of the first wafer, on which the Ru film has been deposited, by use of a solution containing orthoperiodic acid;
(c) patterning, after the step (b), the Ru film on the device side of the first wafer through an etching-resistant mask pattern formed in a lithographic step, thereby forming a capacitor electrode of DRAM;
(d) depositing a film to be processed different in type from the Ru film on a device side of a second wafer among the plurality of wafers passing through the wafer process; and
(e) patterning the film to be processed, which has been deposited on the device side of the second wafer, by the lithographic step.
24. A mass production method of a semiconductor integrated circuit device as recited in 23 above, characterized in that the step of pattering the film to be processed is a lower layer step downstream of or in comparison with the step of patterning the Ru film.
25. A mass production method of a semiconductor integrated circuit device as recited in 24 above, characterized in that the step of patterning the film to be processed is a step of forming a gate electrode or a step of forming a bit line.
26. A mass production method of a semiconductor integrated circuit device as recited in any one of 23 to 25 above, characterized in that the Ru film is removed by use of a solution containing orthoperiodic acid and nitric acid.
27. A mass production method of a semiconductor integrated circuit device as recited in 26 above, characterized in that the solution has a concentration of orthoperiodic acid of 20 wt % to 40 wt %, and a concentration of nitric acid of 20 to 40 wt %.
28. A mass production method of a semiconductor integrated circuit device as recited in 27 above, characterized in that the solution has a concentration of orthoperiodic acid of 25 wt % to 35 wt %, and a concentration of nitric acid of 25 to 35 wt %.
29. A mass production method of a semiconductor integrated circuit device comprising the steps of:
(a) depositing a film containing a transition metal made of a perovskite-type high dielectric material or ferrodielectric material on a device side of a first wafer among a plurality of wafers passing through a wafer process;
(b) removing the transition metal-containing film from outer edge portions of the device side or a back side of the first wafer, on which the transition metal-containing film has been deposited;
(c) patterning, after the step (b), the transition metal-containing film on the device side of the first wafer through an etching-resistant mask pattern formed in a lithographic step, thereby forming a capacitance insulating film of a capacitor of DRAM;
(d) depositing a film to be processed different in type from the transition metal-containing film on a device side of a second wafer among the plurality of wafers passing through the wafer process; and
(e) patterning the film to be processed, which has been deposited on the device side of the second wafer, by the lithographic step.
30. A mass production method of a semiconductor integrated circuit device as recited in 29 above, characterized in that the perovskite-type high dielectric material or ferrodielectric material is made of BST.
The general meanings of the terms used in the present invention are illustrated below.
1. The term xe2x80x9cCMIS integrated circuitxe2x80x9d is intended to mean an integrated circuit made of a complementary insulation gate-type FET including, aside from general CMOS integrated circuits, devices having a gate insulating film made, for example, of a dielectric material other than an oxide film such as silicon nitride or tantalum oxide.
2. The term xe2x80x9cdevice sidexe2x80x9d means a main surface of a wafer, on which an integrated circuit pattern corresponding to a plurality of chip regions is formed by photolithography. That is, xe2x80x9cdevice sidexe2x80x9d is an opposite side of xe2x80x9cback sidexe2x80x9d.
3. The term xe2x80x9cburied wiringxe2x80x9d means one wherein a groove is formed in an insulating film as in single Damascene or dual Damascene, and a conductive film such as copper is buried in the groove, followed by removal of an unnecessary conductive film through patterning by a wiring-forming technique.
4. The term xe2x80x9csemiconductor integrated circuit waterxe2x80x9d or xe2x80x9csemiconductor waferxe2x80x9d is intended to mean a silicon single crystal substrate (usually, substantially in a circular form), a sapphire substrate, a glass substrate, other insulating, anti-insulating and semiconductive substrates, and composite substrates thereof. The term xe2x80x9csemiconductor integrated circuit devicexe2x80x9d (or xe2x80x9celectronic devicexe2x80x9d, xe2x80x9celectronic circuit devicexe2x80x9d and the like) means not only a device formed on a single crystal silicon substrate, but also those devices formed on various types of above-mentioned substrates, or other types of substrates including an SOI (silicon on insulator) substrate, a TFT (thin film transistor) liquid crystal-manufacturing substrate, an STN (super twisted nematic) liquid crystal-manufacturing substrate and the like unless otherwise indicated.
5. The term xe2x80x9cchip-forming portionxe2x80x9d means a portion including a plurality of chip regions on the device side of a wafer, indicating an inner region except xe2x80x9can outer edge portionxe2x80x9d where it is not intended to make a peripheral chipxe2x80x9d.
6. The term xe2x80x9chigh dielectric materialxe2x80x9d means a high dielectric material having a specific inductive capacity of 20 or over, such as Ta2O5, and a high dielectric material having a specific inductive capacity exceeding 100, such as BST ((Ba, Sr)TiO3).
7. The term xe2x80x9cferrodielectric materialxe2x80x9d means PZT, PLT, PLZT, SBT, PbTiO3, SrTiO3 and BaTiO3, which, respectively, have a perovskite structure in a ferrodielectric phase at normal temperatures.
8. The term xe2x80x9ctransition metalxe2x80x9d generally means elements of group 3, to which yttrium, lanthanum and the like belong, to group 11, to which copper and the like belongs, of the periodic table. The term xe2x80x9ctransition metal-containing filmxe2x80x9d means a film which comprises a material containing a transition metal, or a transition metal as a major or minor proportion of an constituent element (e.g. Ru, RuO2, Ta2O5 and the like). The term xe2x80x9ctransition metal-containing film deposition treatmentxe2x80x9d means a treatment wherein the above-mentioned transition metal-containing film is attached to or deposited purposely or unintentionally. Accordingly, the treatment includes, aside from the step of depositing an insulating film or a metal film, an etching step. In the practice of the invention, the term xe2x80x9charmful transition metalxe2x80x9d means one which is not adequately evidenced with respect to the nature as a contaminant among transition metals employed in a semiconductor process and is selected, for example, from platinum and copper group elements. Moreover, the term xe2x80x9cmade of copperxe2x80x9d used herein is not limited to pure copper alone, but includes copper containing other constituent element, additive, impurity and the like in amounts not impeding the function thereof unless otherwise indicated.
9. The term xe2x80x9cplatinum group elementxe2x80x9d generally means ruthenium, rhodium, palladium, osmium, iridium and platinum among the elements generally belonging to the groups 8 to 10 of the periodic table.
10. The term xe2x80x9clower layers stepsxe2x80x9d used in a wafer process means a group of a series of steps including the step of formation of a film to be processed, the step of formation of a resist, the steps of exposure, development and patterning of the film, and the like precedent to an intended step when attention is paid to one wafer. For instance, lower wiring steps are a lower layer process or step in comparison with upper wiring steps. The reverse is called xe2x80x9cupper layer stepsxe2x80x9d. It will be noted that these definitions do not always mean a physical upstream or downstream relationship.
11. The term xe2x80x9clithographic stepxe2x80x9d means that with the case of light exposure, for example, the step covers from the step of coating a photoresist onto a wafer after the step of formation of a given film to the step of exposing the photoresist to light and developing the exposed photoresist (including the baking step, if necessary). The common use relation in the lithographic step means the relation where wafers belonging to different steps pass through a lithographic step made of the same arrangement. In this case, the same arrangement does not include all devices in common use. One of devices, e.g. an exposure device (e.g. a light exposure device, an EB exposure device or the like), may be in common use.
12. The term xe2x80x9cmass productionxe2x80x9d in a wafer line generally means a throughput of approximately 1000 wafers/day. In the practice of the invention, taking the tendency toward a large-sized wafer into account, a throughput of approximately 100 wafers/day is included for the mass production. In this case, it is as a matter of course that the same type of wafer is used for the purpose.
13. The term xe2x80x9cchemical mechanical polishing (CMP)xe2x80x9d generally means one wherein while a surface to be polished is in contact with a polishing pad made of a relatively soft cloth-like sheet material under which a slurry is supplied, they are relatively moved along the surface. Beside, CML (chemical mechanical lapping), in which a surface to be polished is moved relative to the surface of a hard grind stone, may be included in the practice of the invention